1. Field of the Invention
The present invention relates to phase-locked loop circuits and voltage-controlled oscillators. The invention particularly relates to a phase-locked loop circuit which generates a clock signal in synchronization with a reference clock signal, and to a voltage-controlled oscillator which produces oscillations at a frequency according to a control voltage in a frequency range selected from a plurality of frequency ranges of oscillations that can be generated by the oscillator.
2. Description of the Background Art
The phase-locked loop (PLL) circuit has a function of producing oscillations by itself to generate a clock signal, and synchronizing the phase of the clock signal with that of an externally supplied reference clock signal. A clock signal having multiples of the frequency of a reference clock signal can be generated by providing a frequency divider in the loop of the PLL circuit. The PLL circuit is thus utilized as the means for supplying a clock signal stably into a chip or supplying a high-speed clock signal at multiples of the frequency of an input clock signal.
FIG. 8 is a circuit block diagram illustrating a structure of a conventional PLL circuit. Such a PLL circuit is disclosed in, for example, "Design of PLL-Based Clock Generation Circuits" (IEEE JOURNAL OF SOLID-STATE CIRCUITS VOL. SC-22, NO. 2, APRIL, 1987) by DEOG-KYOON JEONG et al.
Referring to FIG. 8, the PLL circuit includes a phase/frequency detector (PFD)+phase difference-current converter (Charge Pump: CP) 101, a loop filter (LPF) 102, and a voltage-controlled oscillator (VCO) 105.
PFD+CP 101 detects the phase difference between an externally supplied reference clock signal CLK and a feedback clock signal CLK', and current according to the phase difference is supplied to LPF 102. LPF 102 includes a resistance element 103 and a capacitor 104, and integrates the current supplied from PFD+CP 101 to generate a control voltage VL. VCO 105 produces oscillations at a frequency according to control voltage VL generated by LPF 102 and supplies clock signal CLK'. Clock signal CLK' from VCO 105 is supplied into a chip via a clock drive and fed back to PFD+CP 101. Clock signal CLK' is thus synchronized with reference clock signal CLK.
The power consumption of a chip has been increasing recently as the operating frequency becomes higher. Any way for operating an internal circuit at a low speed unless a high-speed operation is required would be effective, in order to reduce the power consumption. There are three methods of implementing such a way that will be set forth below.
According to the first method, a plurality of PLL circuits having different lock ranges are provided in a chip. For a high-speed operation, a clock signal with a higher frequency is supplied into the chip via a PLL circuit having a lock range with higher frequencies. For a low-speed operation, a clock signal with a lower frequency is supplied into the chip via a PLL circuit having a lock range with lower frequencies. The lock range refers to a frequency range with which the PLL circuit can be synchronized. The value of the lock range is determined by the frequency range of oscillations that can be produced by the VCO in the PLL circuit.
A problem of the first method is the increase in the layout area resulting in increase in power consumption due to the plurality of PLL circuits provided in the chip including capacitor 104 in LPF 102 that generally has a capacitance of as much as several hundreds pf
According to the second method, a PLL circuit having a wide lock range from a lower frequency to a higher frequency is provided in a chip. For a high-speed operation, a clock signal with a higher frequency is supplied into the chip, and a clock signal with a lower frequency is supplied into the chip for a low-speed operation.
The second method requires that a frequency range of oscillations that can be produced by VCO 105 should be sufficiently wide. In order to increase the frequency range of oscillations that can be generated by VCO 105, gain of VCO 105 (the ratio of increase in oscillation frequency to increase in control voltage VL) should be increased and accordingly the sensitivity of VCO 105 should be enhanced. Generally VCO 105 with high sensitivity is difficult to implement. Further, if the sensitivity of VCO 105 is enhanced, response to a slight change in control voltage VL is accordingly enhanced to increase the influence of noises.
According to the third method, as shown in FIG. 9, a plurality of (two in the figure) VCOs 105 and 106 are provided in a single PLL circuit. VCOs 105 and 106 have different frequency ranges of oscillations that can be produced, and thus generate oscillations at frequencies different from each other in response to control voltage VL. A selector 107 selects one of clock signals CLK1 and CLK2 supplied from VCOs 105 and 106 according to the operation speed of the circuit, supplies the selected clock signal into the chip and the selected clock signal is also fed back to PFD+CP 101.
According to the third method, the layout area and power consumption are smaller compared with the first method according to which a plurality of PLL circuits are provided in the chip. In addition, stability is improved compared with the second method by making the gain of VCOs 105 and 106 equal to each other while there is the difference in the frequency range of oscillations that can be produced between VCO 105 and VCO 106.
However, all of the VCOs 105 and 106 in the PLL circuit in FIG. 9 are always producing oscillations, and unnecessary power is consumed by the VCO supplying a clock signal which is not used.